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2.5 V to 5.5 V Octal Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP AD5308/AD5318/AD5328*
FEATURES AD5308: 8 Buffered 8-Bit DACs in 16-Lead TSSOP A Version: 1 LSB INL, B Version: 0.75 LSB INL AD5318: 8 Buffered 10-Bit DACs in 16-Lead TSSOP A Version: 4 LSB INL, B Version: 3 LSB INL AD5328: 8 Buffered 12-Bit DACs in 16-Lead TSSOP A Version: 16 LSB INL, B Version: 12 LSB INL Low Power Operation: 0.7 mA @ 3 V Guaranteed Monotonic by Design over All Codes Power-Down to 120 nA @ 3 V, 400 nA @ 5 V Double-Buffered Input Logic Buffered/Unbuffered/VDD Reference Input Options Output Range: 0 V to VREF or 0 V to 2 VREF Power-On Reset to 0 V Programmability Individual Channel Power-Down Simultaneous Update of Outputs (LDAC) Low Power, SPI(R), QSPITM, MICROWIRETM, and DSP Compatible 3-Wire Serial Interface On-Chip Rail-to-Rail Output Buffer Amplifiers Temperature Range -40 C to +105 C APPLICATIONS Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Optical Networking Automatic Test Equipment Mobile Communications Programmable Attenuators Industrial Process Control GENERAL DESCRIPTION
The AD5308/AD5318/AD5328 are octal 8-, 10-, and 12-bit buffered voltage output DACs in a 16-lead TSSOP. They operate from a single 2.5 V to 5.5 V supply, consuming 0.7 mA typ at 3 V. Their on-chip output amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7 V/s. The AD5308/AD5318/ AD5328 use a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards. The references for the eight DACs are derived from two reference pins (one per DAC quad). These reference inputs can be configured as buffered, unbuffered, or VDD inputs. The parts incorporate a power-on reset circuit, which ensures that the DAC outputs power up to 0 V and remain there until a valid write to the device takes place. The outputs of all DACs may be updated simultaneously using the asynchronous LDAC input. The parts contain a power-down feature that reduces the current consumption of the devices to 400 nA at 5 V (120 nA at 3 V). The eight channels of the DAC may be powered down individually. All three parts are offered in the same pinout, which allows users to select the resolution appropriate for their application without redesigning their circuit board.
FUNCTIONAL BLOCK DIAGRAM
VDD VREFABCD VDD GAIN-SELECT LOGIC
BUFFER
LDAC
INPUT REGISTER INPUT REGISTER INPUT REGISTER INPUT REGISTER
DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER DAC REGISTER
STRING DAC A STRING DAC B STRING DAC C STRING DAC D STRING DAC E STRING DAC F STRING DAC G STRING DAC H
VOUTA VOUTB VOUTC VOUTD VOUTE VOUTF VOUTG VOUTH
BUFFER
BUFFER
SCLK INTERFACE LOGIC
BUFFER
SYNC
INPUT REGISTER INPUT REGISTER INPUT REGISTER INPUT REGISTER
BUFFER
DIN
BUFFER
BUFFER
BUFFER
POWER-ON RESET LDAC
GAIN-SELECT LOGIC VDD VREFEFGH
POWER-DOWN LOGIC
GND
*Protected by U.S.Patent No. 5,969,657; other patents pending.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved.
AD5308/AD5318/AD5328-SPECIFICATIONS GND; C = 200 pF to GND; all specifications T to T , unless otherwise noted.)
L MIN MAX
(VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 k
to
Parameter1 DC PERFORMANCE AD5308 Resolution Relative Accuracy Differential Nonlinearity AD5318 Resolution Relative Accuracy Differential Nonlinearity AD5328 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Lower Deadband 5 Upper Deadband 5 Offset Error Drift 6 Gain Error Drift 6 DC Power Supply Rejection Ratio 6 DC Crosstalk6 DAC REFERENCE INPUTS 6 VREF Input Range VREF Input Impedance (R DAC)
3, 4
A Version Min Typ
2
Max
Min
B Version2 Typ
Max
Unit
Conditions/Comments
8 0.15 0.02 10 0.5 0.05 12 2 0.2 5 0.30 10 10 -12 -5 -60 200 1.0 0.25 >10.0 37.0 45.0 18.0 22.0 VDD VDD 16 1.0 60 1.25 60 60 4 0.50 1 0.25
8 0.15 0.02 10 0.5 0.05 12 2 0.2 5 0.30 10 10 -12 -5 -60 200 1.0 0.25 37.0 18.0 >10.0 45.0 22.0 -70.0 -75.0 0.001 VDD - 0.001 0.5 25.0 16.0 2.5 5.0 1 0.8 0.8 0.7 1 0.8 0.8 0.7 1.7 3.0 3.0 5.5 1.0 0.7 1.8 1.5 2.5 1.0 0.7 5.5 1.8 1.5 VDD VDD 12 1.0 60 1.25 60 60 3 0.50 0.75 0.25
Bits LSB LSB Bits LSB LSB Bits LSB LSB mV % of FSR mV mV
Guaranteed Monotonic by Design over All Codes
Guaranteed Monotonic by Design over All Codes
Guaranteed Monotonic by Design over All Codes VDD = 4.5 V, Gain = +2. See Figures 2 and 3. VDD = 4.5 V, Gain = +2. See Figures 2 and 3. See Figure 2. Lower deadband exists only if offset error is negative. See Figure 3. Upper deadband exists only if V REF = VDD and offset plus gain error is positive.
ppm of FSR/C ppm of FSR/C dB VDD = 10% V RL = 2 k to GND or VDD V V M k k dB dB V V mA mA s s A V V V V pF V mA mA A A VIH = VDD and VIL = GND All DACs in Unbuffered Mode. In Buffered mode, extra current is typically x A per DAC; x = (5 A + VREF/RDAC)/4. VIH = VDD and VIL = GND Buffered Reference Mode Unbuffered Reference Mode Buffered Reference Mode and Power-Down Mode Unbuffered Reference Mode. 0 V to V REF Output Range. Unbuffered Reference Mode. 0 V to 2 V REF Output Range. Frequency = 10 kHz Frequency = 10 kHz This is a measure of the minimum and maximum drive capability of the output amplifier. VDD = 5 V VDD = 3 V Coming Out of Power-Down Mode. V DD = 5 V. Coming Out of Power-Down Mode. V DD = 3 V.
Reference Feedthrough Channel-to-Channel Isolation OUTPUT CHARACTERISTICS 6 Minimum Output Voltage 7 Maximum Output Voltage 7 DC Output Impedance Short Circuit Current Power-Up Time LOGIC INPUTS 6 Input Current VIL, Input Low Voltage
-70.0 -75.0 0.001 VDD - 0.001 0.5 25.0 16.0 2.5 5.0
VIH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode) 8 VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V IDD (Power-Down Mode) 9 VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V
1.7
VDD = 5 V 10% VDD = 3 V 10% VDD = 2.5 V VDD = 2.5 V to 5.5 V; TTL and CMOS Compatible
2.5
0.4 0.12
1 1
0.4 0.12
1 1
NOTES 1 See the Terminology section. 2 Temperature range (A, B Version): -40C to +105C; typical at +25C. 3 DC specifications tested with the outputs unloaded unless stated otherwise. 4 Linearity is tested using a reduced code range: AD5308 (Code 8 to Code 255), AD5318 (Code 28 to Code 1023), and AD5328 (Code 115 to Code 4095). 5 This corresponds to x codes. x = deadband voltage/LSB size. 6 Guaranteed by design and characterization; not production tested. 7 For the amplifier output to reach its minimum voltage, offset error must be negative; for the amplifier output to reach its maximum voltage, V REF = VDD and offset plus gain error must be positive. 8 Interface inactive. All DACs active. DAC outputs unloaded. 9 All eight DACs powered down. Specifications subject to change without notice.
-2-
REV. B
AD5308/AD5318/AD5328 AC CHARACTERISTICS1
Parameter
2
(VDD = 2.5 V to 5.5 V; RL = 2 k otherwise noted.)
A, B Version3 Min Typ Max 6 7 8 0.7 12 0.5 0.5 1 3 200 -70 8 9 10
to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless
Unit s s s V/s nV-s nV-s nV-s nV-s nV-s kHz dB
Conditions/Comments VREF = VDD = 5 V 1/4 Scale to 3/4 Scale Change (0x40 to 0xC0) 1/4 Scale to 3/4 Scale Change (0x100 to 0x300) 1/4 Scale to 3/4 Scale Change (0x400 to 0xC00) 1 LSB Change around Major Carry
Output Voltage Settling Time AD5308 AD5318 AD5328 Slew Rate Major-Code Change Glitch Energy Digital Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion
VREF = 2 V 0.1 V p-p. Unbuffered Mode. VREF = 2.5 V 0.1 V p-p. Frequency = 10 kHz.
NOTES 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range (A, B Version): -40C to +105C; typical at +25C. Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2, 3
Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 A, B Version Limit at TMIN, TMAX 33 13 13 13 5 4.5 0 50 20 20 0 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Conditions/Comments SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Falling Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC High Time LDAC Pulsewidth SCLK Falling Edge to LDAC Rising Edge SCLK Falling Edge to LDAC Falling Edge
NOTES 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2. 3 See Figures 2 and 3. Specifications subject to change without notice.
t1
SCLK
t8
SYNC
t4 t6 t5
t3
t2
t7
DIN
DB15
DB0
t9 t11
LDAC 1
t10
LDAC 2
NOTES 1 ASYNCHRONOUS LDAC UPDATE MODE 2 SYNCHRONOUS LDAC UPDATE MODE
Figure 1. Serial Interface Timing Diagram
REV. B
-3-
AD5308/AD5318/AD5328
ABSOLUTE MAXIMUM RATINGS 1, 2
(TA = 25C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Digital Input Voltage to GND . . . . . . . -0.3 V to VDD + 0.3 V Reference Input Voltage to GND . . . . -0.3 V to VDD + 0.3 V VOUTA-VOUTD to GND . . . . . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (A, B Version) . . . . . . . . . . . . . -40C to +105C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature (TJ MAX) . . . . . . . . . . . . . . . . . . . 150C
16-Lead TSSOP Power Dissipation . . . . . . . . . . . . . . . . . . . (TJ MAX - TA)/ JA JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4C/W Reflow Soldering Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Model AD5308ARU AD5308ARU-REEL7 AD5308BRU AD5308BRU-REEL AD5308BRU-REEL7 AD5318ARU AD5318ARU-REEL7 AD5318BRU AD5318BRU-REEL AD5318BRU-REEL7 AD5318BRUZ* AD5318BRUZ-REEL* AD5318BRUZ-REEL7* AD5328ARU AD5328ARU-REEL7 AD5328BRU AD5328BRU-REEL AD5328BRU-REEL7
*Z = Pb-free part.
Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C
Package Description Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP)
Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5308/AD5318/AD5328 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
-4-
REV. B
AD5308/AD5318/AD5328
PIN CONFIGURATION
LDAC 1 SYNC 2 VDD 3 VOUTA 4 16 SCLK
13 VOUTH TOP VIEW 12 VOUTG (Not to Scale) VOUTC 6 11 VOUTF VOUTB 5 VOUTD 7 VREFABCD 8 10 VOUTE 9 VREFEFGH
AD5308/ AD5318/ AD5328
15 DIN 14 GND
PIN FUNCTION DESCRIPTIONS
Pin No. 1
Mnemonic LDAC
Function This active low-control input transfers the contents of the input registers to their respective DAC registers. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low. Active Low-Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND. Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Reference Input Pin for DACs A, B, C, and D. It may be configured as a buffered, unbuffered, or VDD input to the four DACs, depending on the state of the BUF and VDD control bits. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Reference Input Pin for DACs E, F, G, and H. It may be configured as a buffered, unbuffered, or VDD input to the four DACs, depending on the state of the BUF and VDD control bits. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Buffered Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
2
SYNC
3 4 5 6 7 8
VDD VOUTA VOUTB VOUTC VOUTD VREFABCD
9
VREFEFGH
10 11 12 13 14 15 16
VOUTE VOUTF VOUTG VOUTH GND DIN SCLK
REV. B
-5-
AD5308/AD5318/AD5328
TERMINOLOGY Relative Accuracy Major-Code Transition Glitch Energy
For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. Typical INL versus code plots can be seen in TPCs 1, 2, and 3.
Differential Nonlinearity
Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11).
Digital Feedthrough
Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL versus code plots can be seen in TPCs 4, 5, and 6.
Offset Error
Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device, but is measured when the DAC is not being written to (SYNC held high). It is specified in nV-s and is measured with a fullscale change on the digital input pins, i.e., from all 0s to all 1s and vice versa.
Digital Crosstalk
This is a measure of the offset error of the DAC and the output amplifier (see Figures 2 and 3). It can be negative or positive, and is expressed in mV.
Gain Error
This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range.
Offset Error Drift
This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-s.
Analog Crosstalk
This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/C.
Gain Error Drift
This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/C.
DC Power Supply Rejection Ratio (PSRR)
This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s.
DAC-to-DAC Crosstalk
This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V and VDD is varied 10%.
DC Crosstalk
This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in V.
Reference Feedthrough
This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s.
Multiplying Bandwidth
This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (i.e., LDAC is high). It is expressed in dB.
Channel-to-Channel Isolation
The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion
This is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in dB.
This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in dB.
-6-
REV. B
AD5308/AD5318/AD5328
GAIN ERROR AND OFFSET ERROR
OUTPUT VOLTAGE GAIN ERROR AND OFFSET ERROR UPPER DEADBAND CODES
OUTPUT VOLTAGE
ACTUAL IDEAL POSITIVE OFFSET ERROR DAC CODE
NEGATIVE OFFSET ERROR
DAC CODE ACTUAL IDEAL
FULL SCALE
Figure 3. Transfer Function with Positive Offset
LOWER DEADBAND CODES AMPLIFIER FOOTROOM
NEGATIVE OFFSET ERROR
Figure 2. Transfer Function with Negative Offset (VREF = VDD)
REV. B
-7-
AD5308/AD5318/AD5328-Typical Performance Characteristics
1.0 TA = 25 C VDD = 5V 0.5
3 TA = 25 C VDD = 5V 2
INL ERROR (LSB)
12 TA = 25 C VDD = 5V
8 INL ERROR (LSB)
INL ERROR (LSB)
1
4 0
0
0 -1
-4
-0.5
-2
-8 -12
0 200 400 600 CODE 800 1000
-1.0
0
50
100
150 CODE
200
250
-3
0
1000
2000 CODE
3000
4000
TPC 1. AD5308 Typical INL Plot
TPC 2. AD5318 Typical INL Plot
TPC 3. AD5328 Typical INL Plot
0.3
TA = 25 C VDD = 5V
0.6
TA = 25 C VDD = 5V
1.0
0.2
DNL ERROR (LSB) DNL ERROR (LSB)
0.4
0.5 DNL ERROR (LSB)
TA = 25 C VDD = 5V
0.1
0.2
0
0
0
-0.1
-0.2 -0.4 -0.6 0
-0.5
-0.2
-0.3
0
50
100 150 CODE
200
250
200
400 600 CODE
800
1000
-1.0 0
1000
2000 CODE
3000
4000
TPC 4. AD5308 Typical DNL Plot
TPC 5. AD5318 Typical DNL Plot
TPC 6. AD5328 Typical DNL Plot
0.50
VDD = 5V TA = 25 C
0.5 0.4
MAX INL
1.0
VDD = 5V VREF = 3V
0.3 0.2
ERROR (LSB)
MAX DNL
MAX INL
VDD = 5V VREF = 2V
0.25
0.5
0.1 0 -0.1
MIN DNL MAX DNL
ERROR (% FSR)
ERROR (LSB)
GAIN ERROR
0
MIN DNL
0
OFFSET ERROR
-0.2
-0.25
MIN INL
-0.5
-0.3
MIN INL
-0.4
-0.50 0 1 2 3 VREF (V) 4 5
-0.5
40
0
40
80
120
-1.0
40
0
40
80
120
TEMPERATURE ( C)
TEMPERATURE ( C)
TPC 7. AD5308 INL and DNL Error vs. VREF
TPC 8. AD5308 INL Error and DNL Error vs. Temperature
TPC 9. AD5308 Offset Error and Gain Error vs. Temperature
-8-
REV. B
AD5308/AD5318/AD5328
0.2 0.1 0
ERROR (% FSR) 5 1.0 5V SOURCE 3V SOURCE 0.9 0.8 0.7 VDD = 5V TA = 25 C
TA = 25 C VREF = 2V
4
GAIN ERROR
VOUT (V)
3 0.6 0.5 0.4 0.3 1 5V SINK 3V SINK 0.2 0.1
-0.1 -0.2 -0.3 -0.4 -0.5 -0.6 OFFSET ERROR
2
0
1
2
3 VDD (V)
4
5
6
0
IDD (mA)
0 2 5 1 3 4 SINK/SOURCE CURRENT (mA) 6
0
ZERO SCALE HALF SCALE FULL SCALE
DAC CODE
TPC 10. Offset Error and Gain Error vs. VDD
TPC 11. VOUT Source and Sink Current Capability
TPC 12. Supply Current vs. DAC Code
1.3 TA = 25 C 1.2 1.1 VREF = 2V, GAIN = +1, BUFFERED
1.0 0.9 0.8 IDD POWER-DOWN ( A) 0.7
IDD (mA)
1.4
TA = 25 C
1.3
DECREASING INCREASING 1.2 1.1 1.0 0.9 0.8 0.7 VDD = 3V
TA = 25 C VDD = 5V
VREF = V DD
IDD (mA)
1.0 0.9 0.8 0.7 0.6 2.0 VREF = 2V, GAIN = +1, UNBUFFERED VREF = V DD, GAIN = +1, UNBUFFERED
0.6 0.5 0.4 0.3 0.2 0.1
2.5
3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V)
5.0
0 2.0
2.5
3.0
3.5 4.0 VDD (V)
4.5
5.0
5.5
0.6 0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VLOGIC (V)
TPC 13. Supply Current vs. Supply Voltage
TPC 14. Power-Down Current vs. Supply Voltage
TPC 15. Supply Current vs. Logic Input Voltage for SCLK and DIN Increasing and Decreasing
TA = 25 C 5s VDD = 5V VREF = 5V VOUTA
TA = 25 C VDD = 5V VREF = 2V VDD CH1
TA = 25 C VDD = 5V VREF = 2V VOUTA CH1
CH1
SCLK
CH2 CH2 VOUTA
PD CH2
CH1 1V, CH2 5V, TIME BASE = 1 s/DIV
CH1 2.00V, CH2 200mV, TIME BASE = 200 s/DIV
CH1 500mV, CH2 5.00V, TIME BASE = 1 s/DIV
TPC 16. Half-Scale Settling (1/4 to 3/4 Scale Code Change)
TPC 17. Power-On Reset to 0 V
TPC 18. Exiting Power-Down to Midscale
REV. B
-9-
AD5308/AD5318/AD5328
35 30 25
FREQUENCY
2.50 SS = 300 VDD = 3V VDD = 5V
MEAN: 0.693798 MEAN: 1.02055
10 0 -10 -20
dB
2.49
20 15 10 5 0
VOUT (V)
-30 2.48 -40 -50 2.47 -60 10
0.6
0.7
0.8
0.9 IDD (mA)
1.0
1.1
1 s/DIV
100
1k 10k 100k FREQUENCY (Hz)
1M
10M
TPC 19. IDD Histogram with VDD = 3 V and VDD = 5 V
TPC 20. AD5328 Major-Code Transition Glitch Energy
TPC 21. Multiplying Bandwidth (Small-Signal Frequency Response)
0.02 VDD = 5V TA = 25 C
FULL-SCALE ERROR (V)
0.01
0
-0.01
-0.02
0
1
2
3 VREF (V)
4
5
6
1mV/DIV
100ns/DIV
TPC 22. Full-Scale Error vs. VREF
TPC 23. DAC-to-DAC Crosstalk
-10-
REV. B
AD5308/AD5318/AD5328
FUNCTIONAL DESCRIPTION
The AD5308/AD5318/AD5328 are octal resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits, respectively. Each contains eight output buffer amplifiers and is written to via a 3-wire serial interface. They operate from single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/s. DACs A, B, C, and D share a common reference input, V REFABCD. DACs E, F, G, and H share a common reference input, VREFEFGH. Each reference input may be buffered to draw virtually no current from the reference source, may be unbuffered to give a reference input range from 0.25 V to V DD, or may come from VDD. The devices have a powerdown mode in which all DACs may be turned off individually with a high impedance output.
Digital-to-Analog Section
R R R TO OUTPUT AMPLIFIER
R R
Figure 5. Resistor String
DAC Reference Inputs
The architecture of one DAC channel consists of a resistorstring DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference voltage for the corresponding DAC. Figure 4 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by
VOUT = VREF x D 2N
There is a reference pin for each quad of DACs. The reference inputs can be buffered from VDD, or unbuffered. The advantage with the buffered input is the high impedance it presents to the voltage source driving it. However, if the unbuffered mode is used, the user can have a reference voltage as low as 0.25 V and as high as VDD since there is no restriction due to the headroom and footroom of the reference amplifier. If there is a buffered reference in the circuit (e.g., REF192), there is no need to use the on-chip buffers of the AD5308/AD5318/ AD5328. In unbuffered mode, the input impedance is still large at typically 45 k per reference input for 0 V to VREF mode and 22 k for 0 V to 2 VREF mode.
Output Amplifier
where D = decimal equivalent of the binary code that is loaded to the DAC register: 0-255 for AD5308 (8 bits) 0-1023 for AD5318 (10 bits) 0-4095 for AD5328 (12 bits) N = DAC resolution
VREFABCD VDD REFERENCE BUFFER GAIN MODE (GAIN = 1 OR 2)
The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on the value of VREF, the gain of the output amplifier, the offset error, and the gain error. If a gain of 1 is selected (GAIN bit = 0), the output range is 0.001 V to VREF. If a gain of 2 is selected (GAIN bit = 1), the output range is 0.001 V to 2 VREF. Because of clamping, however, the maximum output is limited to VDD - 0.001 V. The output amplifier is capable of driving a load of 2 k to GND or VDD, in parallel with 500 pF to GND or VDD. The source and sink capabilities of the output amplifier can be seen in the plot in TPC 11.
VDD
BUF
INPUT REGISTER
DAC REGISTER
RESISTOR STRING OUTPUT BUFFER AMPLIFIER
VOUTA
The slew rate is 0.7 V/s with a half-scale settling time to 0.5 LSB (at eight bits) of 6 s.
POWER-ON RESET
Figure 4. Single DAC Channel Architecture
Resistor String
The AD5308/AD5318/AD5328 are provided with a power-on reset function so that they power up in a defined state. The power-on state is * * * * * Normal operation Reference inputs unbuffered 0 V to VREF output range Output voltage set to 0 V LDAC bits set to LDAC high
The resistor-string section is shown in Figure 5. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up.
REV. B
-11-
AD5308/AD5318/AD5328
SERIAL INTERFACE Table I. Address Bits for the AD53x8
The AD5308/AD5318/AD5328 are controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards.
Input Shift Register
A2 (Bit 14) 0 0 0 0 1 1 1 1
A1 (Bit 13) 0 0 1 1 0 0 1 1
A0 (Bit 12) 0 1 0 1 0 1 0 1
DAC Addressed DAC A DAC B DAC C DAC D DAC E DAC F DAC G DAC H
The input shift register is 16 bits wide. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is shown in Figure 1. The SYNC input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the device only while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC to SCLK falling edge setup time, t4. After SYNC goes low, serial data will be shifted into the device's input shift register on the falling edges of SCLK for 16 clock pulses. To end the transfer, SYNC must be taken high after the falling edge of the 16th SCLK pulse, observing the minimum SCLK falling edge to SYNC rising edge time, t7. After the end of serial data transfer, data will automatically be transferred from the input shift register to the input register of the selected DAC. If SYNC is taken high before the 16th falling edge of SCLK, the data transfer will be aborted and the DAC input registers will not be updated. Data is loaded MSB first (Bit 15). The first bit determines whether it is a DAC write or a control function.
DAC Write
Control Functions
In the case of a control function, the MSB (Bit 15) will be a 1. This is followed by two control bits, which determine the mode. There are four different control modes, each of which is described below. The write sequences for these modes are shown in Table II.
Reference and Gain Mode
This mode determines whether the reference for each group of DACs is buffered, unbuffered, or from VDD. It also determines the gain of the output amplifier. To set up the reference of both groups, set the control bits to (00), set the GAIN bits, set the BUF bits, and set the VDD bits. BUF Controls whether the reference of a group of DACs is buffered or unbuffered. The reference of the first group of DACs (A, B, C, and D) is controlled by setting Bit 2, and the second group of DACs (E, F, G, and H) is controlled by setting Bit 3. 0: Unbuffered reference. 1: Buffered reference.
Here, the 16-bit word consists of one control bit and three address bits followed by 8, 10, or 12 bits of DAC data, depending on the device type. In the case of a DAC write, the MSB will be a 0. The next three address bits determine whether the data is for DAC A, DAC B, DAC C, DAC D, DAC E, DAC F, DAC G, or DAC H. The AD5328 uses all 12 bits of DAC data. The AD5318 uses 10 bits and ignores the two LSBs. The AD5308 uses eight bits and ignores the last four bits. These ignored LSBs should be set to 0. The data format is straight binary, with all 0s corresponding to 0 V output and all 1s corresponding to full-scale output.
GAIN The gain of the DACs is controlled by setting Bit 4 for the first group of DACs (A, B, C, and D) and Bit 5 for the second group of DACs (E, F, G, and H). 0: Output range of 0 V to VREF. 1: Output range of 0 V to 2 VREF.
BIT 15 (MSB) D/C A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0
BIT 0 (LSB) 0
DATA BITS
Figure 6. AD5308 Input Shift Register Contents
BIT 15 (MSB) D/C A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 BIT 0 (LSB) 0
DATA BITS
Figure 7. AD5318 Input Shift Register Contents
BIT 15 (MSB) D/C A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 BIT 0 (LSB) D0
DATA BITS
Figure 8. AD5328 Input Shift Register Contents
-12-
REV. B
AD5308/AD5318/AD5328
Table II. Control Words for the AD53x8
D/C 15 1 1 1 1
Control Bits 14 13 12 0 0 1 0 1 0 x x x
11 x x x
10 9 x x x x x x x x
8 x x x x
7 x x H x
6 x x
5
4
3
2
1
0
Mode Gain of Output Amplifier and Reference Selection LDAC Power-Down Reset
(GAIN Bits) E..H A..D x x
(BUF Bits) E..H A..D x D x x C x
(VDD Bits) E..H A..D (LDAC Bits) 1/0 1/0 B x A x
(Channels) GF E x x x
(RESET) 1 1
1/0 x
VDD
These bits are set when VDD is to be used as reference. The first group of DACs (A, B, C, and D) can be set up to use VDD by setting Bit 0, and the second group of DACs (E, F, G, and H) by setting Bit 1. The VDD bits have priority over the BUF bits. When VDD is used as the reference, it will always be unbuffered and with an output range of 0 V to VREF, regardless of the state of the GAIN and BUF bits.
Reset Mode
This mode consists of two possible reset functions, as outlined in Table IV.
Table IV. Reset Mode
Bit 15 1 1
Bit 14 1 1
Bit 13 1 1
Bit 12 0 1
Bit 11 .... 0 x .... x x .... x
Description DAC Data Reset Data and Control Reset
LDAC Mode
LDAC mode controls LDAC, which determines when data is transferred from the input registers to the DAC registers. There are three options when updating the DAC registers, as shown in Table III.
Table III. LDAC Mode
DAC Data Reset: On completion of this write sequence, all DAC registers and input registers are filled with 0s. Data and Control Reset: This function carries out a DAC data reset and also resets all the control bits (GAIN, BUF, VDD, LDAC, and power-down channels) to their power-on conditions.
Low Power Serial Interface
Bit 15 1 1 1 1
Bit 14 0 0 0 0
Bit 13 1 1 1 1
Bits 12 .... 2 x ..... x x ..... x x ..... x x ..... x
Bit 1 0 0 1 1
Bit 0 0 1 0 1
Description LDAC Low LDAC High LDAC Single Update Reserved
To minimize the power consumption of the device, the interface powers up fully only when the device is being written to, i.e., on the falling edge of SYNC. The SCLK and DIN input buffers are powered down on the rising edge of SYNC.
LOAD DAC INPUT (LDAC) FUNCTION
LDAC Low (00): This option sets LDAC permanently low, allowing the DAC registers to be updated continuously. LDAC High (01): This option sets LDAC permanently high. The DAC registers are latched, and the input registers may change without affecting the contents of the DAC registers. This is the default option for this mode. LDAC Single Update (10): This option causes a single pulse on LDAC, updating the DAC registers once. Reserved (11): Reserved.
Power-Down Mode
Access to the DAC registers is controlled by both the LDAC pin and the LDAC mode bits. The operation of the LDAC function can be likened to the configuration shown in Figure 9.
EXTERNAL LDAC PIN LDAC FUNCTION INTERNAL LDAC MODE
Figure 9. LDAC Function
The individual channels of the AD5308/AD5318/AD5328 can be powered down separately. The control mode for this is (10). On completion of this write sequence, the channels that have been set to 1 are powered down.
REV. B
-13-
AD5308/AD5318/AD5328
If the user wishes to update the DAC through software, the LDAC pin should be tied high and the LDAC mode bits set as required. Alternatively, if the user wishes to control the DAC through hardware, i.e., the LDAC pin, the LDAC mode bits should be set to LDAC high (default mode). Use of the LDAC function enables double-buffering of the DAC data, and the GAIN, BUF and VDD bits. There are two ways in which the LDAC function can operate: Synchronous LDAC: The DAC registers are updated after new data is read in on the falling edge of the 16th SCLK pulse. LDAC can be permanently low or pulsed as in Figure 1. Asynchronous LDAC: The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the DAC registers are updated with the contents of the input register.
DOUBLE-BUFFERED INTERFACE
The bias generator, the output amplifiers, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. In fact, it is possible to load new data to the input registers and DAC registers during power-down. The DAC outputs will update as soon as the device comes out of power-down mode. The time to exit power-down is typically 2.5 s for VDD = 5 V and 5 s when VDD = 3 V.
AMPLIFIER RESISTORSTRING DAC VOUT
POWER-DOWN CIRCUITRY
Figure 10. Output Stage during Power-Down
The AD5308/AD5318/AD5328 DACs all have double-buffered interfaces consisting of two banks of registers: input and DAC. The input registers are connected directly to the input shift register, and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC registers contain the digital code used by the resistor strings. When the LDAC pin is high and the LDAC bits are set to (01), the DAC registers are latched and the input registers may change state without affecting the contents of the DAC registers. However, when the LDAC bits are set to (00) or when the LDAC pin is brought low, the DAC registers become transparent and the contents of the input registers are transferred to them. The double-buffered interface is useful if the user requires simultaneous updating of all DAC outputs. The user may write to seven of the input registers individually and then, by bringing LDAC low when writing to the remaining DAC input register, all outputs will update simultaneously. These parts contain an extra feature whereby a DAC register is not updated unless its input register has been updated since the last time LDAC was low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5308/AD5318/AD5328, the part will update the DAC register only if the input register has been changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk.
POWER-DOWN MODE
MICROPROCESSOR INTERFACING ADSP-2101/ADSP-2103 to AD5308/AD5318/AD5328 Interface
Figure 11 shows a serial interface between the AD5308/AD5318/ AD5328 and the ADSP-2101/ADSP-2103. The ADSP-2101/ ADSP-2103 should be set up to operate in the SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: internal clock operation, active-low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. The data is clocked out on each rising edge of the DSP's serial clock and clocked into the AD5308/AD5318/ AD5328 on the falling edge of the DAC's SCLK.
ADSP-2101/ ADSP-2103*
AD5308/ AD5318/ AD5328*
SYNC DIN SCLK
TFS DT SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. ADSP-2101/ADSP-2103 to AD5308 AD5318/AD5328 Interface
68HC11/68L11 to AD5308/AD5318/AD5328 Interface
The AD5308/AD5318/AD5328 have low power consumption, typically dissipating 2.4 mW with a 3 V supply and 5 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into power-down mode, which was described previously. When in default mode, all DACs work normally with a typical power consumption of 1 mA at 5 V (800 A at 3 V). However, when all DACs are powered down, i.e., in power-down mode, the supply current falls to 400 nA at 5 V (120 nA at 3 V). Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier, making it open-circuit. This has the advantage that the output is threestate while the part is in power-down mode, and provides a defined input condition for whatever is connected to the output of the DAC amplifier. The output stage is illustrated in Figure 10.
Figure 12 shows a serial interface between the AD5308/AD5318/ AD5328 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5308/AD5318/ AD5328, while the MOSI output drives the serial data line (DIN) of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for the correct operation of this interface are as follows: the 68HC11/68L11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5308/AD5318/AD5328, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure. REV. B
-14-
AD5308/AD5318/AD5328
68HC11/68L11*
AD5308/ AD5318/ AD5328*
SYNC SCLK DIN
APPLICATIONS Typical Application Circuit
PC7 SCK MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. 68HC11/68L11 to AD5308/AD5318/ AD5328 Interface
80C51/80L51 to AD5308/AD5318/AD5328 Interface
The AD5308/AD5318/AD5328 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0.25 V to VDD. More typically, these devices are used with a fixed, precision reference voltage. Suitable references for 5 V operation are the AD780, ADR381, and REF192 (2.5 V references). For 2.5 V operation, a suitable external reference would be the AD589 and AD1580 (1.2 V band gap references). Figure 15 shows a typical setup for the AD5308/AD5318/AD5328 when using an external reference.
VDD = 2.5V TO 5.5V 10 F VREFABCD 1F VREFEFGH VOUTA VOUTB
Figure 13 shows a serial interface between the AD5308/AD5318/ AD5328 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/80L51 drives SCLK of the AD5308/AD5318/AD5328, while RxD drives the serial data line of the part. The SYNC signal is again derived from a bit programmable pin on the port. In this case, port line P3.3 is used. When data is transmitted to the AD5308/AD5318/ AD5328, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in a format that has the LSB first. The AD5308/AD5318/AD5328 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account.
80C51/80L51*
VIN VOUT EXT REF
0.1 F
AD780/ADR3811/REF192 WITH VDD = 5V OR AD589/AD1580 WITH VDD = 2.5V
AD5308/AD5318/ AD5328
SCLK DIN SYNC GND VOUTG VOUTH
SERIAL INTERFACE
Figure 15. AD5308/AD5318/AD5328 Using a 2.5 V External Reference
Driving VDD from the Reference Voltage
AD5308/ AD5318/ AD5328*
SYNC SCLK DIN
P3.3 TxD RxD
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. 80C51/80L51 to AD5308/AD5318/ AD5328 Interface
MICROWIRE to AD5308/AD5318/AD5328 Interface
If an output range of 0 V to VDD is required when the reference inputs are configured as unbuffered, the simplest solution is to connect the reference input to VDD. As this supply may be noisy and not very accurate, the AD5308/AD5318/AD5328 may be powered from a voltage reference. For example, using a 5 V reference, such as the REF195, will work because the REF195 will output a steady supply voltage for the AD5308/AD5318/ AD5328. The typical current required from the REF195 is a 1 A supply current and 112 A into the reference inputs (if unbuffered); this is with no load on the DAC outputs. When the DAC outputs are loaded, the REF195 also needs to supply the current to the loads. The total current required (with a 10 k load on each output) is 1.22 mA + 8(5V / 10 k) = 5.22 mA The load regulation of the REF195 is typically 2.0 ppm/mA, which results in an error of 10.4 ppm (52 V) for the 5.22 mA current drawn from it. This corresponds to a 0.003 LSB error at eight bits and 0.043 LSB error at 12 bits.
Bipolar Operation Using the AD5308/AD5318/AD5328
Figure 14 shows an interface between the AD5308/AD5318/ AD5328 and any MICROWIRE compatible device. Serial data is shifted out on the falling edge of the serial clock, SK, and is clocked into the AD5308/AD5318/AD5328 on the rising edge of SK, which corresponds to the falling edge of the DAC's SCLK.
MICROWIRE*
AD5308/ AD5318/ AD5328*
SYNC SCLK DIN
CS SK SO
The AD5308/AD5318/AD5328 have been designed for singlesupply operation, but a bipolar output range is also possible using the circuit in Figure 16. This circuit will give an output voltage range of 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820, the AD8519, or an OP196 as the output amplifier.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14. MICROWIRE to AD5308/AD5318/ AD5328 Interface
REV. B
-15-
AD5308/AD5318/AD5328
5V +6V TO +16V 10 F 0.1 F VDD VIN VOUTA R1 10k 5V
10k SCLK SCLK
R2 10k 5V
POWER
5V REGULATOR
10 F
0.1 F
VDD
REF192
VOUT GND 1F
AD5308/AD5318/ AD5328
VREFABCD VREFEFGH GND VOUTB VOUTC
AD820/ AD8519/ -5V OP196
VDD VREFABCD VREFEFGH
VDD 10k
AD5308/AD5318/ AD5328
VOUTA SYNC VOUTB VOUTC VOUTD
VOUTH
SYNC
DIN SCLK SYNC
SERIAL INTERFACE
10k
VDD
VOUTE VOUTF DIN GND VOUTG VOUTH
Figure 16. Bipolar Operation with the AD5308/ AD5318/AD5328
DIN
The output voltage for any input code can be calculated as follows:
REFIN x D 2N x ( R1 + R2) VOUT = R1 - REFIN x ( R2 / R1)
where D is the decimal equivalent of the code loaded to the DAC. N is the DAC resolution. REFIN is the reference voltage input. with REFIN = 5 V, R1 = R2 = 10 k:
(
)
Figure 17. AD5308/AD5318/AD5328 in an Opto-Isolated Interface
Decoding Multiple AD5308/AD5318/AD5328s
VOUT = 10 x D / 2N - 5V
Opto-Isolated Interface for Process Control Applications
(
)
The SYNC pin on the AD5308/AD5318/AD5328 can be used in applications to decode a number of DACs. In this application, the DACs in the system receive the same serial clock and serial data but only the SYNC to one of the devices will be active at any one time, allowing access to four channels in this 16-channel system. The 74HC139 is used as a 2-to-4 line decoder to address any of the DACs in the system. To prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded-address inputs are changing state. Figure 18 shows a diagram of a typical setup for decoding multiple AD5308 devices in a system.
AD5308
SCLK DIN VDD VCC ENABLE CODED ADDRESS 1G 74HC139 1Y0 1A 1Y1 1Y2 1B 1Y3 DGND SYNC DIN SCLK VOUTA VOUTB
The AD5308/AD5318/AD5328 have a versatile 3-wire serial interface, making them ideal for generating accurate voltages in process control and industrial applications. Due to noise, safety requirements, or distance, it may be necessary to isolate the AD5308/AD5318/AD5328 from the controller. This can easily be achieved by using opto-isolators that will provide isolation in excess of 3 kV. The actual data rate achieved may be limited by the type of optocouplers chosen. The serial loading structure of the AD5308/AD5318/AD5328 makes them ideally suited for use in opto-isolated applications. Figure 17 shows an opto-isolated interface to the AD5308/AD5318/AD5328 where DIN, SCLK, and SYNC are driven from optocouplers. The power supply to the part also needs to be isolated. This is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5308/AD5318/ AD5328.
VOUTG VOUTH
AD5308
VOUTA VOUTB SYNC DIN SCLK
VOUTG VOUTH
AD5308
VOUTA VOUTB SYNC DIN SCLK
VOUTG VOUTH
AD5308
VOUTA VOUTB SYNC DIN SCLK
VOUTG VOUTH
Figure 18. Decoding Multiple AD5308 Devices in a System
-16-
REV. B
AD5308/AD5318/AD5328
Table V. Overview of AD53xx Serial Devices
Part No. SINGLES AD5300 AD5310 AD5320 AD5301 AD5311 AD5321 DUALS AD5302 AD5312 AD5322 AD5303 AD5313 AD5323 QUADS AD5304 AD5314 AD5324 AD5305 AD5315 AD5325 AD5306 AD5316 AD5326 AD5307 AD5317 AD5327 OCTALS AD5308 AD5318 AD5328
Resolution
DNL 0.25 0.50 1.00 0.25 0.50 1.00 0.25 0.50 1.00 0.25 0.50 1.00 0.25 0.50 1.00 0.25 0.50 1.00 0.25 0.50 1.00 0.25 0.50 1.00 0.25 0.50 1.00
VREF Pins 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 0 (VREF = VDD) 2 2 2 2 2 2
Settling Time ( s)
Interface
Package
Pins
8 10 12 8 10 12
4 6 8 6 7 8
SPI SPI SPI 2-Wire 2-Wire 2-Wire
SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP
6, 8 6, 8 6, 8 6, 8 6, 8 6, 8
8 10 12 8 10 12
6 7 8 6 7 8
SPI SPI SPI SPI SPI SPI
MSOP MSOP MSOP TSSOP TSSOP TSSOP
10 10 10 16 16 16
8 10 12 8 10 12 8 10 12 8 10 12
1 1 1 1 1 1 4 4 4 2 2 2
6 7 8 6 7 8 6 7 8 6 7 8
SPI SPI SPI 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire SPI SPI SPI
MSOP MSOP MSOP MSOP MSOP MSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
10 10 10 10 10 10 16 16 16 16 16 16
8 10 12
2 2 2
6 7 8
SPI SPI SPI
TSSOP TSSOP TSSOP
16 16 16
Visit www.analog.com/support/standard_linear/selection_guides/AD53xx.html for more information.
Table VI. Overview of AD53xx Parallel Devices
Part No. SINGLES AD5330 AD5331 AD5340 AD5341 DUALS AD5332 AD5333 AD5342 AD5343 QUADS AD5334 AD5335 AD5336 AD5344 REV. B
Resolution 8 10 12 12 8 10 12 12 8 10 10 12
DNL 0.25 0.50 1.00 1.00 0.25 0.50 1.00 1.00 0.25 0.50 0.50 1.00
VREF Pins 1 1 1 1 2 2 2 1 2 2 4 4
Settling Time ( s) 6 7 8 8 6 7 8 8 6 7 7 8 -17-
Additional Pin Functions BUF GAIN HBEN CLR
Package TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
Pins 20 20 24 20 20 24 28 20 24 24 28 28

AD5308/AD5318/AD5328
OUTLINE DIMENSIONS 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16)
Dimensions shown in millimeters
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
0.15 0.05
COMPLIANT TO JEDEC STANDARDS MO-153AB
-18-
REV. B
AD5308/AD5318/AD5328 Revision History
Location 11/03--Data Sheet changed from REV. A to REV. B. Page
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to Y axis on TPCs 12, 13, and 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
8/03--Data Sheet changed from REV. 0 to REV. A.
Added A Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
REV. B
-19-

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